<junari>
I'll rebase the code for ddr3 and push it today
<apritzel>
junari: awesome, many thanks!
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<apritzel>
jernej: looking at the BROM disassembly, it's not the H6 hotplug method (via the RTC), but the H616 version, just at a different address: magic at 0x70501c0, address at 0x70501c4
<apritzel>
though it still doesn't work :-(
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<apritzel>
ah, but with that BL31 trampoline replacement it works from SD card, on the Avaota
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<junari>
after the latest driver changes there are discrepancies in the output of register dumps, but the DRAM looks working
<junari>
apritzel: Explain a little more how to repeat your success? I changed the value in fel_utils.S, also tried to build a jump file instead of bl31 as you said before, but I failed.
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<apritzel_>
the board pictured in the Wiki doesn't have the SPI flash soldered, but instead packs an eMMC chip
<wigyori>
apritzel_: thx - haven't looked at it yet -, seems that it's supported out-of-tree, but i guess it's not known yet if it's hooked up via usb or sdio
<apritzel_>
wigyori: pretty surely via SDIO. The same chip is used on the X96QPro+ TV box, and it's SDIO there
<wigyori>
gotcha, thx
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<jernej>
apritzel: any chance that you share nbrom bin? I have troubles dumping it
<jernej>
apritzel: I think reset to aarch32 works just fine. If you replace back_to_32 address with 0x20, I get USB disconnect error, which is expected.
<jernej>
apritzel: thanks!
<apritzel>
I dumped it a while ago, from my A523 tablet, I think using memcpy from some code I uploaded via FEL
<apritzel>
I think the BROM area doesn't support byte accesses, but readl worked for me via FEL
<apritzel>
it's just tedious ;-)
<jernej>
wait, is this secure or non-secure brom?
<apritzel>
I named it sbrom.bin, because the tablet requires TOC0, and I dumped it from there
<jernej>
ah, ok
<jernej>
base address is still 0?
<apritzel>
yes
<apritzel>
there is another region called MBROM starting at 64K
<apritzel>
at least that's what the manual says
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<jernej>
apritzel: correct me if I'm wrong, but at the beginning BROM clears part of SRAM where SPL return to FEL trampoline would reside
<apritzel>
that was also an angle I was looking at: yes, it clears 0x44000-0x64000
<apritzel>
but I think it's clearing that only for FEL entry, right, so when entered at 0x20?
<apritzel>
on reset it branches to 0x44, which clears all GPRs (why?), then ungates the RTC (@0x250), then does some bit shuffling with an RTC register, then checks the hotplug register
<jernej>
ah, right
<jernej>
hm... or maybe it works but something inadvertently broke USB? since I get "usb_bulk_send() ERROR -9: Pipe error"
<apritzel>
you mean some of the clock setups? or this NSI init?
<jernej>
yeah
<jernej>
hm... doesn't seem so
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