<ity>
A new Allwinner board is out since December (A733), has anyone looked at it ?
<ity>
It has a stub on the wiki
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<jernej>
ity: which one?
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<hlauer>
<apritzel> "NC pins are sometimes detectable..." <- Indeed PH23 can be pulled up on M2U V1.0 going high and not on V1.1. So V1.1 is detectable
<hlauer>
should V1.1 get an own DT file, as also the buildin mmc chip needs to be handled differently?
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<ity>
jernej: What is the exact question ? Ah, we meant the SoC, if the confusion is about us saying board out of habit
<jernej>
ah, ok, I was hopping there is proper A733 SBC to play with :)
<ity>
Same, it's why we are asking here if anyone knows of any haha
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<jernej>
apritzel: This is only difference that I found between H728 and T527 BROM (in green): https://ibb.co/dm5t1yx
<jernej>
but this couldn't be the issue, otherwise 32-bit SPL hack couldn't work and there must be also something else
<jernej>
however, this shows that at least these two SoCs are not exactly the same. Maybe different stepping?
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<apritzel>
jernej: I am actually suspecting sunxi-fel now: I think the addresses in soc_info.c might still not be right? And maybe the LPDDR4 init uses more stack than the DDR3, so this makes the difference?
<apritzel>
I spent last night looking at all the remaining GIC state, and even restoring ICC_IGRPEN0 and ICC_MGRPEN1 didn't help, so I don't think it's the GIC at fault anymore
<jernej>
apritzel: I don't think LPDDR4 takes any more stack than DDR3. I even try to return to FEL before DRAM is initialized, but it still didn't work.
<apritzel>
ity: I have a tablet with that SoC, and got it into FEL, but am busy with other stuff atm
<apritzel>
ity: there are signs of an "Avaota NAS" with the A733 in Syterkit, so I guess that's a board from Yuzuki coming out soon?
<jernej>
apritzel: I also replaced aarch32 address with 0x44000, but it didn't show any SPL bootloop
<apritzel>
jernej: is your diff really from the BROM? Why does it bother with the DRAM PLL and gate clock at all?
<jernej>
yes, because even your sbrom has same code, just without green part
<jernej>
I have no idea, it was part of crypto engine clock setup routine
<apritzel>
my plan was to double check the SRAM usage: basically spray something over as much of the SRAM as I can, then run the SPL, and then check afterwards what has survived
<jernej>
ah, that's a great plan
<apritzel>
I did this with some simple code before, but not with the full SPL, in particular not with a full DRAM init
<apritzel>
jernej: I also figured that the Avaota FEL works much better if I hold the FEL button for longer, so a few seconds rather than just one, but not sure if that's the root cause or not
<apritzel>
(the root cause for my Avaota get-to-FEL issues, I mean)
<jernej>
ah, I don't use that button much, because I either boot without sd card or SPL actually somehow manages to reboot and that naturally falls back to FEL
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<loki666>
jernej: so far no more detection issues
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<jernej>
loki666: ok, so I'll make proper patch for that
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