ChanServ changed the topic of #asahi-gpu to: Asahi Linux GPU development (no user support, NO binary reversing) | Keep things on topic | GitHub: https://alx.sh/g | Wiki: https://alx.sh/w | Logs: https://alx.sh/l/asahi-gpu
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<i509vcb> what does the bool return value mean for nir passes?
<alyssa> i509vcb: Typically, whether the pass made "progress"
<alyssa> ~= if the pass made any change to the shader
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<alyssa> i509vcb: ella-0: Mary: I've rebased AGXV with the new uapi, it's in alyssa/mesa:agxv/rebase
<alyssa> when the new kernel ships (very soon) I'll push that to agxv/main
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<i509vcb> Before I reinvent the wheel, is there some sort of accepted way to do a sort of read only pass over nir?
<i509vcb> Well... I already reinvented the wheel, but it could be square
<i509vcb> Over nir as in the entire shader
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<alyssa> i509vcb: nir_Shader_instructions_pass and just return fals
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<alyssa> ella-0: i509vcb: Mary: agxv/main is now rebased on top of the latest UAPI, which is now shipping in both the fedora remix and the arch
<alyssa> so bump to the latest agxv/main and upgrade your system and you should be synced
<alyssa> no need to build your own kernel, I hope
<Mary> Time for some kernel upgrade~
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<Mary> deqp-vk seems to be running fine so I guess everything landed on fedora ^^
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<alyssa> :)
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<i509vcb> agxv seemed to be fine after the upgrade, although I am a bit deep into sysval stuff in agxv
<alyssa> i509vcb: nice!
<alyssa> btw after the rebase, the load_texture_base_agx sysval goes away, because it's unimplementable on Vulkan
<alyssa> in its place, AGXV is required to use bindless texture/image instructions (rather than non-bindless ones using the index to denote a texture state register) when the backend says so
<alyssa> once you hook that up in lower_descriptor_sets, textureSize() should Just Work
<i509vcb> I guess I wonder where do I throw the passes to replace the intrinsics for things like load_num_workgroups with loads from uniform registers
<alyssa> agx_pipeline, for now
<i509vcb> Well relative to the rest of the passes
<alyssa> who cares
<alyssa> i mean
<i509vcb> Sounds about right
<alyssa> shrug
<alyssa> "the passes" probably you want a single pass for all the sysvals
<i509vcb> Conceptually I guess I can just consider the whole thing one pass even though I do a sort of inner pass to figure out what sysvals need to be lowered and another inner pass to actually lower
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<alyssa> sure
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<i509vcb> what does the "base" mean in load_preamble?
<i509vcb> register index of sorts?
<alyssa> i509vcb: uniform register index
<alyssa> in 16-bit units
<alyssa> 32 %0 = load_preamble (base=10)
<alyssa> means
<alyssa> 0 = mov u5
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<i509vcb> Just to confirm, it not possible to do unaligned reads? i.e. read a 32-bit value from u1h and u2l
<i509vcb> but for a 64-bit value, it appears the two registers just need to be neighbors? (u4 and u3 for example?)