#asahi-dev on 2025-03-03 — irc logs at oftc.irclog.whitequark.org

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06:58 <nickchan> and on a7-a11, t2 there will always be preloader stages before m1n1, there are some stuff like kernel and iboot patching, SEP ROM firmware load races that require binary RE, no way around it, some parts even call hardcoded function pointers in SecureROM to setup a USB stack while subject to strict size limitations

06:58 <nickchan> that stuff doesn't belong to here :)

06:59 <nickchan> (kernel patching mostly for assisting with dynamic tracing)

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07:05 <nickchan> at least I hope I don't have to shove seprom fwload race into Linux

07:05 <nickchan> but SEP interface is unstable

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07:06 <nickchan> can probably make it work by setting up a shellcode firmware loading interface from the preloader stages

07:07 <nickchan> make loading sep firmware work from Linux I mean

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11:37 <nickchan> chaos_princess: did you ever got around to poking voltage registers on t8103?

11:37 <chaos_princess> sorry, no, slipped my mind. will do later

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15:13 <alyssa> jannau: oops, right, yes

15:13 <alyssa> on my todo list, top priority for agx

15:13 <alyssa> s/agx/asahi/

15:13 <alyssa> hopefully will get to it today

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21:02 <chaos_princess> nickchan: so, uh, what registers did you want me to try overwriting?

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23:38 <nickchan> chaos_princess: cluster->base + 0x70000 + off + pstate * 0x20

23:39 <nickchan> off includes 0x0, 0x8, 0x10, 0x18 it covers the entire pstate definitions

23:40 <nickchan> so like to overwrite pstate 3 with pstate 4

23:40 <nickchan> write64(cluster->base + 0x70000 + 0x0 + 3 * 0x20, read64(cluster->base + 0x70000 + 0x0 + 4 * 0x20))

23:40 <nickchan> write64(cluster->base + 0x70000 + 0x8 + 3 * 0x20, read64(cluster->base + 0x70000 + 0x8 + 4 * 0x20))

23:40 <nickchan> write64(cluster->base + 0x70000 + 0x10 + 3 * 0x20, read64(cluster->base + 0x70000 + 0x10 + 4 * 0x20))

23:40 <nickchan> write64(cluster->base + 0x70000 + 0x18 + 3 * 0x20, read64(cluster->base + 0x70000 + 0x18 + 4 * 0x20))

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23:41 <nickchan> the last one doesn't actually exist on a11 but i think it exists in m1 as the strides becomes 0x40 in m2 which probably means apple run out of space

23:42 <nickchan> and now cpu_pstate_latencies and such should report pstate 3 and 4 being the same

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23:57 <nickchan> at least according to adt /arm-io/pmgr for t6000 it's also cluster->base + 0x70000